1. Field Of The Invention
The present invention relates to a transport interface for time division frames, in particular SDH frames, and related interfacing method of time division frames.
2. Description Of The Prior Art
In modern digital communication systems, the various information streams, or data, propagating on telecommunication networks are multiplexed in frames according to predetermined transport protocols, such as SDH (Synchronous Digital Hierarchy) transport protocol for time division frames. This transport protocol is particularly suitable for conveying and distributing the numerous information streams among the various telecommunications network nodes.
Therefore, various logic circuits are arranged inside the telecommunications network nodes, such as SDH network, apt to process in different ways the time division frame received from the node. These operations are essentially related to dealing with the synchronism and with the extraction of the various data streams multiplexed inside the time division frame, as well as with the subsequent processing of the various information streams extracted from said time division frames.
Therefore, in order to process the SDH time division frame, an ASIC (Application Specific Integrated Circuit) circuit, i.e. a dedicated circuit is developed, which performs SDH operations on the frame by extracting and inserting the information streams, also called tributaries, from the so called Virtual Containers, wherein they are multiplexed. This ASIC circuit can be followed by FPGA (Field Programmable Gate Arrays) circuits, i.e. circuits adaptable according to their utilization and located outside the ASIC circuit, which process the tributaries extracted from the frame, such as processing the streams that use ATM (Asynchronous Transfer Mode) protocol or IP (Internet Protocol) protocol, previously multiplexed inside the SDH frame. Due to their flexibility, FPGA circuits are frequently employed in conjunction with dedicated circuits.
Communications between ASIC circuits and related FPGA circuits are usually defined as ‘intra-equipment’ communications, namely communications occurring inside the telecommunications network node, whereas communications between the nodes are called line communications. The same interface protocols employed for the nodes receiver interfaces are also used for the above intraequipment communications of tributaries, such as the so called Network Node Interfaces, i.e. network node interfaces for line communications to other nodes.
This causes some drawbacks, since the tributaries are sent to FPGA devices under a very complex structure defined by SDH protocol, which is redundant compared with the needs, and requires the use of complex interfaces between the FPGA devices and ASIC circuit.
Moreover, the interfaces of the ASIC circuit are not flexible, since they have to operate on different protocols, i.e. ATM or IP, which are not structure compatible. For instance, an ASIC circuit can communicate with a certain number of FPGA devices performing certain termination functions, e.g. operating according to ATM protocol, but cannot communicate with FPGA devices using IP protocol, unless they have further transport interfaces expressly provided for handling IP protocol available. This reduces ASIC circuit flexibility.